Conventionally, design of an LSI circuit is roughly classified into three hierarchies of function design, signal connection of a hierarchical logic circuit, and layout design thereof. The function design produces a circuit of a register transfer level (RTL) from a function to be realized. The signal connection of a hierarchical logic circuit produces a net list of a logic gate from the RTL circuit. The layout design produces a mask pattern from the net list. Generally, in order to perform the signal connection of a hierarchical logic circuit efficiently, a hardware description language (HDL) is used to perform logic synthesis or logic verification. In recent years, an LSI circuit has been increasingly larger. However, when the HDL becomes large, amount of time taken for the logic synthesis or the logic verification increases, and readability of the HDL lowers. Consequently, it has been required to divide the logic circuit by functions to hierarchize the same. The HDL of the hierarchized logic circuit can describe only connection of a signal in a hierarchy. That is, the HDL of the hierarchized logic circuit cannot directly describe connection of a signal outside the hierarchy. Consequently, in order to perform signal connection between hierarchies, a hierarchy port is produced, and the connection is described via the hierarchy port. Conventionally, when the signal connection between hierarchies (connection of a net or a pin) is performed, as shown in FIG. 31, procedures of
(1) production of a hierarchy port 300;
(2) connection between a net 302 or a pin in a hierarchy and the hierarchy port 300; and
(3) connection between a net 304 or a pin outside a hierarchy and the hierarchy port 300 must be performed.
Patent Literature 1: JP-A-2002-56041
However, in such a conventional method for connecting a signal between hierarchies, the above three procedures of (1) to (3) must be clearly indicated in order to perform connection of a signal between hierarchies. Further, when the hierarchy port is produced, an input/output attribute showing that the hierarchy port is an input port or an output port must be also clearly indicated. Since this procedure is often manually performed, an error may be included. Further, when the above three procedures of (1) to (3) are intended to be simply automated, it can be thought that, when there is a plurality of targets to be connected, a plurality of hierarchy ports are produced. FIG. 32A shows a case in which there are two nets 304, 306 outside a hierarchy with respective to a net 302 in the hierarchy, and in this case, two hierarchy ports 300-1, 300-2 are produced and connected. However, such production of the plurality of hierarchy ports may not be allowed depending on a design rule. In this case, it is desired to produce only one hierarchy port 300 and perform connection, as shown in FIG. 33.